The 74HC595 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The "595" is an 8-stage serial shift register with a storage
register and 3-state outputs. The shift register and storage
register have separate clocks.
Data is shifted on the positive-going transitions of the
SH CP input. The data in each register is transferred to the
storage register on a positive-going transition of the ST CP
input. If both clocks are connected together, the shift
register will always be one clock pulse ahead of the
storage register.
The shift register has a serial input (D S ) and a serial
standard output (Q 7 ') for cascading. It is also provided with
asynchronous reset (active LOW) for all 8 shift register
stages. The storage register has 8 parallel 3-state bus
driver outputs. Data in the storage register appears at the
output whenever the output enable input (OE) is LOW.

? 8-bit serial input
? 8-bit serial or parallel output
? Storage register with 3-state outputs
? Shift register with direct clear
? 100 MHz (typ) shift out frequency
? Output capability:
- parallel outputs; bus driver
- serial output; standard
? I CC category: MSI.